The present invention disclosed herein relates to a delta-sigma modulator, and more particularly, to a clock timing adjustment device for adjusting a time difference of clocks and a delta-sigma modulator adopting the same.
A delta-sigma modulator is a signal converter using an analog-to-digital or digital-to-analog modulation method derived from a delta modulation method. Although this method has already been proposed in the early 1960s, it is being widely used for a wire-wireless communication with the advancement of semiconductor technology. Since a delta-sigma modulator is suitable for a multiple communication and makes it possible to implement a low-power system, the delta-sigma modulator is used for the wire-wireless communication.
Typically, the delta-sigma modulator includes circuit blocks of a Continuous Time (CT)-integrator, a Digital to Analog Converter (DAC), and a quantizer. Each circuit block generates a delay time between input and output signals. The delay time of each circuit block greatly degrades stability of the delta-sigma modulator. Particularly, it is important to compensate the delay time generated by the CT-integrator and the DAC for preventing degradation of stability and performance of the delta-sigma modulator.